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B.Tech Course
Digital Electronics
Digital Electronics
Curriculum
12 Sections
37 Lessons
45 Hours
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Module 1: Field Effect Transistors & Applications
7
1.1
1.1 Junction Field Effect Transistors (JFETs)
1.2
1.2 Metal Oxide Semiconductor FETs (MOSFETs)
1.3
1.3 Differences between JFETs and MOSFETs
1.4
1.4 Biasing MOSFETs
1.5
1.5 FET Applications in amplifiers & switching
1.6
1.6 CMOS Devices and applications
1.7
1.7 Wave-shaping circuits: IC Multivibrators (Astable, Monostable, Bistable)
Module 2: Operational Amplifiers & Applications
4
2.1
2.1 Introduction to Operational Amplifier
2.2
2.2 Ideal vs. Practical Op-amp characteristics
2.3
2.3 Performance Parameters of Op-amps (CMRR, Slew rate, etc.)
2.4
2.4 Applications of Op-amp
Module 3: Logic Gates & Combinational Circuits
4
3.1
3.1 Basic Gates review
3.2
3.2 Positive & Negative Logic
3.3
3.3 Introduction to HDL
3.4
3.4 Combinational Logic Design
Module 4: Data Processing & Sequential Circuits
12
4.1
4.1 Multiplexers & Demultiplexers
4.2
4.2 1-of-16 Decoder, BCD to Decimal Decoder
4.3
4.3 Seven Segment Decoder, Encoders
4.4
4.4 Exclusive-OR gates, Parity Generators & Checkers
4.5
4.5 Magnitude Comparator
4.6
4.6 Programmable Array Logic (PAL), Programmable Logic Array (PLA)
4.7
4.7 HDL Implementation of Data Processing Circuits
4.8
4.8 RS, JK, D Flip-Flops (Edge Triggered & Master-Slave)
4.9
4.9 Flip-Flop Timing, Switch Bounce Circuits
4.10
4.10 Representations of Flip-Flops in HDL
4.11
4.11 Registers: SISO, SIPO, PISO, PIPO, Universal Shift Register
4.12
4.12 Applications of Shift Registers
Module 5: Counters & Data Conversion
10
5.1
5.1 Asynchronous & Synchronous Counters
5.2
5.2 Decoding Gates
5.3
5.3 Changing Counter Modulus
5.4
5.4 Decade Counters, Presettable Counters
5.5
5.5 Counter Design as a Synthesis Problem
5.6
5.6 Digital Clock design
5.7
5.7 HDL Implementation of Counters
5.8
5.8 Digital-to-Analog Conversion (Resistor Networks, Binary Ladders, Accuracy & Resolution)
5.9
5.9 Analog-to-Digital Conversion (Simultaneous, Counter Method, Continuous, Dual-slope)
5.10
5.10 A/D Converter techniques, Accuracy & Resolution
LAB1: Verification and interpretation of truth table for AND, OR, NOT, NAND, NOR, Ex-OR, Ex-NOR gates
0
LAB 2: Construction of half and full adder using XOR and NAND gates and verification of its operation
0
LAB 3: To Study and Verify Half and Full Subtractor
0
LAB 4: Verify the truth table of RS, JK, T and D flip-flops using NAND and NOR gates
0
LAB 5: Implementation of 4x1 multiplexer and 1x4 demultiplexer using logic gates
0
LAB 6: Design and verify the 4- Bit Synchronous or Asynchronous Counter using JK Flip Flop
0
LAB 7: Design a synchronous up/down counter
0
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