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Courses
5G
5G L2 Stack Mastery
Curriculum
4 Sections
101 Lessons
20 Hours
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5G L2 MAC
50
1.1
RACH Procedures in 5G NR
11 Minutes
1.2
Major Enhancements in 5G NR RACH
12 Minutes
1.3
EDT Scenario-TS 38.321,38.300,38.331
7 Minutes
1.4
Preamble Format Categories & Their Impact
3 Minutes
1.5
RACH FLOW
45 Minutes
1.6
5G NR PRACH Power Control
5 Minutes
1.7
5G NR RA-RNTI Calculation(TS 38.321)
6 Minutes
1.8
MAC structure for RAR
18 Minutes
1.9
5G Timing Advance TS 38.321
8 Minutes
1.10
Downlink and Uplink Timing Relation TS 38.321
9 Minutes
1.11
Physical Layer Timing Unit(Tc)
6 Minutes
1.12
How Timing Advance Command is applied
4 Minutes
1.13
Example Calculation_RAR TA
4 Minutes
1.14
MSG3 PUSCH time domain resource Allocation
6 Minutes
1.15
MSG3 Frequency Domain Resource Allocation
1.16
MAC BSR
6 Minutes
1.17
Types of BSR
20 Minutes
1.18
BSR Formats
5 Minutes
1.19
BSR MAC-CE Structure
4 Minutes
1.20
BSR Type Selection Example
6 Minutes
1.21
5G RLF (TS 38.321)
14 Minutes
1.22
BFR TS 38.321 5.17
10 Minutes
1.23
RRC Parameters for Beam Failure Detection
3 Minutes
1.24
RRC Parameters for Beam Failure Recovery TS 38.331
9 Minutes
1.25
HARQ Entities and Processes
12 Minutes
1.26
Key Procedures
4 Minutes
1.27
Retransmissions
7 Minutes
1.28
HARQ Feedback Handling
10 Minutes
1.29
Buffer Management
3 Minutes
1.30
Synchronization and State Variables
6 Minutes
1.31
Purpose of SR
3 Minutes
1.32
SR Configuration
13 Minutes
1.33
Triggering Conditions
5 Minutes
1.34
SR Transmission Procedure
7 Minutes
1.35
SR Procedure Fallback and Co-ordination
15 Minutes
1.36
Purpose of PHR
6 Minutes
1.37
Types of PHR
3 Minutes
1.38
Triggering Conditions
7 Minutes
1.39
PHR Procedure
1.40
Purpose of DRX
9 Minutes
1.41
DRX Configuration
11 Minutes
1.42
Bandwidth Part (BWP) Operation
8 Minutes
1.43
BWP Types
24 Minutes
1.44
BWP Configuration
5 Minutes
1.45
BWP Activation & Deactivation
11 Minutes
1.46
BWP Switching Triggers
12 Minutes
1.47
MAC-Layer Procedures
12 Minutes
1.48
Key Differences from LTE
4 Minutes
1.49
Hands On: BWP Switching DCI 1_1 validation
22 Minutes
1.50
Hands On: RLC Log analysis Deep Drive Amarisoft Test Bed
5G L2 RLC
20
2.1
Functionality 38.322 4.4
2.2
Functionality TM
2.3
Functionality UM
2.4
Functionality AM
2.5
Q&A
2.6
RRC Parameters defining RLC
2.7
PDU Transmission Order in RLC UM 38.322 6.2.2.3
2.8
PDU Transmission Order in RLC AM 38.322 6.2.2.4
2.9
RLC Max Transmission
2.10
RLC Window Stall
2.11
Why Half the Max Window Length?
2.12
STATUS PDU 38.322 6.2.2.5
2.13
ARQ procedures 38.322 5.3
2.14
Polling Mechanism Logic & Trigger Conditions
2.15
Example Scenario
2.16
Why Periodic Polling?
2.17
SDU discard procedures 38.322 5.4
2.18
Components Included in Data Volume
2.19
Calculation Rules
2.20
Hands On: RLC Log analysis Deep Drive Amarisoft Test Bed
5G L2 PDCP
24
3.1
Transfer of Data (User Plane & Control Plane)
9 Minutes
3.2
Maintenance of PDCP Sequence Numbers (SNs)
6 Minutes
3.3
Header Compression & Decompression (ROHC)
9 Minutes
3.4
Ciphering & Deciphering (Encryption)
7 Minutes
3.5
Integrity Protection & Verification
5 Minutes
3.6
Timer-Based SDU Discard
4 Minutes
3.7
PDU Set Discard
4 Minutes
3.8
Routing (Split Bearers & DAPS Bearer)
3.9
Duplication
5 Minutes
3.10
Reordering & In-Order Delivery
6 Minutes
3.11
Duplicate Discarding
2 Minutes
3.12
PDCP layer, functional view(TS 38.323 4.2.2)
3.13
Services (TS 38.323 4.3.1)
15 Minutes
3.14
Robust header compression and decompression TS 38.323 5.7
19 Minutes
3.15
ROHC Modes in 5G: Unidirectional Mode (U-mode)
3.16
U-mode PCAP validation
3 Minutes
3.17
Bidirectional Optimistic Mode (O-mode)- TS 38.323/RFC 3095
6 Minutes
3.18
Bidirectional Reliable Mode (R-mode)
6 Minutes
3.19
Header decompression using ROHC Flow Diagram (TS 38.323 5.7.5)
15 Minutes
3.20
Ciphering and deciphering Deep Drive (TS 38.323 5.8)
22 Minutes
3.21
Integrity Protection and Verification Deep Drive (TS 38.323 5.9)
38 Minutes
3.22
PDCP Data Structure (TS 38.323 6.2.2/6.2.3)
13 Minutes
3.23
PDCP Structure Parameter (TS 38.323 6.3)
22 Minutes
3.24
Hands On: PDCP Log analysis Deep Drive Amarisoft Test Bed
Production-Level C++ Coding Exercises
7
4.1
HARQ Process Logic
4.2
MAC Scheduler Concepts
4.3
RACH Handling Logic
4.4
Buffer Management
4.5
PDCP SN Management
4.6
Reordering Mechanisms
4.7
State Machine Handling
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